Selected publications

2008

  • WCET-Driven, Code-Size Critical Procedure Cloning (PDF, 410kB)
    By Paul Lokuciejewski, Heiko Falk, and Peter Marwedel, TU Dortmund, and Henrik Theiling, AbsInt.
    In: The 11th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2008.
  • WCET-Driven Cache-Based Procedure Positioning Optimizations (PDF, 230kB)
    By Paul Lokuciejewski, Heiko Falk, and Peter Marwedel, TU Dortmund.
    In: The 20th Euromicro Conference on Real-Time Systems (ECRTS) 2008.
  • A Retargetable Framework for Multi-Objective WCET-Aware High-Level Compiler Optimizations (PDF, 100kB)
    By Sascha Plazar, Paul Lokuciejewski, and Peter Marwedel, TU Dortmund.
    In: The 29th IEEE Real-Time Systems Symposium (RTSS) WiP 2008.
  • A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine (PDF, 270kB)
    By Luca Benini, Michele Lombardi, Michela Milano, and Martino Ruggiero, University of Bologna.
    In: CP 2008.
  • Multi-Stage Benders Decomposition for Optimizing Multicore Architectures
    By Luca Benini, Michele Lombardi, Michela Milano, Martino Ruggiero, and Marco Mantovani, University of Bologna.
    In: CPAIOR 2008.
  • Resource-Management Policy Handling Multiple Use Cases in MPSoC Platforms Using Constraint Programming
    By Luca Benini, Davide Bertozzi, and Michela Milano, University of Bologna.
    In: ICLP 2008.
  • Cellflow: a Parallel Application Development Environment with Run-Time Support for the Cell BE Processor (PDF, 380kB)
    By Martino Ruggiero, Michele Lombardi, Michela Milano, and Luca Benini, University of Bologna.
    In: 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD) 2008.
  • Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology
    By Andrea Marongiu and others, University of Bologna.
    In: Proceedings of EUROMICRO 2008.
  • A Framework for Designing Embedded Real-Time Controllers
    By Yifan Wu, Enrico Bini, and Giorgio Buttazzo, Scuola Superiore Sant’Anna.
    In: RCTSA 2008.
  • Parametric Timing Analysis for Complex Architectures
    By Sebastian Altmeyer, Björn Lisper, and Reinhard Wilhelm, Saarland University, and Christian Hümbert, AbsInt.
    In: Proceedings of the 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) 2008.
  • CAMA: Cache-Aware Memory Allocation for WCET Analysis
    By Jörg Herter, Jan Reineke, and Reinhard Wilhelm, Saarland University.
    In: Proceedings Work-In-Progress Session of the 20th Euromicro Conference on Real-Time Systems, 2008.
  • WCET Analysis for Preemptive Systems
    By Sebastian Altmeyer and Gernot Gebhard, Saarland University.
    In: Proceedings of the 8th International Workshop on Worst-Case Execution Time (WCET) Analysis, 2008.
  • Estimating the Performance of Cache Replacement Policies
    By Daniel Grund and Jan Reineke, Saarland University.
    In: MEMOCODE 2008: Proceedings of the 6th IEEE/ACM International Conference on Formal Methods and Models for Code Design.
  • Relative Competitiveness of Cache Replacement Policies
    By Jan Reineke and Daniel Grund, Saarland University.
    In: SIGMETRICS 2008: Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems.
  • Relative Competitive Analysis of Cache Replacement Policies
    By Jan Reineke and Daniel Grund, Saarland University.
    In: LCTES 2008: Proceedings of the 2008 ACM SIGPLAN–SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems.
  • Abstract Interpretation with Applications to Timing Validation (PDF, 180kB)
    By Reinhard Wilhelm and Björn Wachter, Saarland University.
    In: CAV 2008: Proceedings of the 20th International Conference on Computer Aided Verification.
  • A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness
    By Martino Ruggiero and others, University of Bologna.
    In: International Journal of Parallel Programming, 36 (1), 2008.
  • Energy-Efficient Task Partition for Periodic Real-Time Tasks on Platforms with Dual Processing Elements
    By Jian-Jia Chen and others, ETH Zurich.
    In: Proceedings of ICPADS 2008.
  • Expected System Energy Consumption Minimization in Leakage-Aware DVS Systems
    By Jian-Jia Chen and others, ETH Zurich.
    In: Proceedings of ISLPED 2008.
  • Optimistic Reliability-Aware Energy Management for Real-Time Tasks with Probabilistic Execution Times
    By Dakai Zhu, University of Texas at San Antonio, Hakan Aydin, George Mason University, and Jian-Jia Chen, ETH Zurich.
    In: Proceedings of the 2008 Real-Time Systems Symposium (RTSS).
  • Sensitivity Analysis for Fixed-Priority Real-Time Systems
    By Enrico Bini, Marco Di Natale, and Giorgio Buttazzo, Scuola Superiore Sant’Anna.
    In: Real-Time Systems, 39 (1), 2008.
  • Timing Validation of Automotive Software
    By Daniel Kästner and others, AbsInt.
    In: ISoLA 2008.

2009

  • Accelerating WCET-Driven Optimizations by the Invariant Path Paradigm — a Case Study of Loop Unswitching
    By Paul Lokuciejewski and others, TU Dortmund.
    In: Proceedings of SCOPES 2009.
  • A Fast and Precise Static Loop Analysis Based on Abstract Interpretation, Program Slicing, and Polytope Models
    By Paul Lokuciejewski, Daniel Cordes, Heiko Falk, and Peter Marwedel, TU Dortmund.
    In: Code Generation and Optimization (CGO) 2009.
  • Automatic WCET Reduction by Machine Learning Based Heuristics for Function Inlining
    By Paul Lokuciejewski, Fatih Gedikli, Peter Marwedel, and Katharina Morik, TU Dortmund.
    In: The 3rd Workshop on Statistical and Machine Learning Approaches to Architectures and Compilation (SMART) 2009.
  • A New Notion of Useful Cache Block to Improve the Bounds of Cache-Related Preemption Delay
    By Sebastian Altmeyer and others, Saarland University.
    In: Proceedings of ECRTS 2009.
  • Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization
    By Paul Lokuciejewski and others, TU Dortmund.
    In: Proceedings of ECRTS 2009.
  • A Precedence Constraint Posting Approach for the RCPSP with Time Lags and Variable Durations
    By Michele Lombardi and others, University of Bologna.
    In: Proceedings of CP 2009.
  • Abstract Interpretation of FIFO Replacement
    By Daniel Grund and others, Saarland University.
    In: Proceedings of SAS 2009.
  • Adaptive Dynamic Power Management for Hard Real-Time Systems
    By Kai Huang and others, ETH Zurich.
    In: Proceedings of RTSS 2009.
  • Feasibility Analysis of On-Line DVS Algorithms for Scheduling Arbitrary Event Streams
    By Jian-Jia Chen and others, ETH Zurich.
    In: Proceedings of RTSS 2009.
  • An Approximation Scheme for Energy-Efficient Scheduling of Real-Time Tasks in Heterogeneous Multiprocessor Systems
    By Chuan-Yue Yang and Tei-Wei Kuo, National Taiwan University, and Jian-Jia Chen and Lothar Thiele, ETH Zurich.
    In: Proceedings of DATE 2009.
  • Reliable Mode Changes in Real-Time Systems with Fixed Priority or EDF Scheduling
    By Nikolay Stoimenov and others, ETH Zurich.
    In: Proceedings of DATE 2009.
  • Branch Target Buffers: WCET Analysis and Timing Predictability
    By Daniel Grund and others, Saarland University.
    In: Proceedings of RTCSA 2009.
  • Robust Non-Preemptive Hard Real-Time Scheduling for Clustered Multicore Platforms
    By Michele Lombardi and others, University of Bologna.
    In: Proceedings of DATE 2009.
  • Cache-Related Preemption Delay Computations for Set-Associative Caches — Pitfalls and Solutions
    By Claire Burguière, Jan Reineke, and Sebastian Altmeyer, Saarland University.
    In: Proceedings of WCET 2009.
  • Computing the Maximum Blocking Time for Scheduling with Deferred Preemption
    By Sebastian Altmeyer and others, Saarland University.
    In: Proceedings of STFSSD 2009.
  • Energy Minimization for Periodic Real-Time Tasks on Heterogeneous Processing Units
    By Jian-Jia Chen and others, ETH Zurich.
    In: Proceedings of IPDPS 2009.
  • Improving Timing Analysis for MATLAB Simulink/Stateflow
    By Lili Tan and others, Saarland University.
    In: Proceedings of ACES-MB 2009.
  • Making Dynamic Memory Allocation Static to Support WCET Analyses
    By Jörg Herter and Jan Reineke, Saarland University.
    In: Proceedings of WCET 2009.
  • Sound and Efficient WCET Analysis in the Presence of Timing Anomalies
    By Jan Reineke and others, Saarland University.
    In: Proceedings of WCET 2009.
  • WCET-Aware Software-Based Cache Partitioning for Multi-Task Real-Time Systems
    By Sascha Plazar and others, TU Dortmund.
    In: Proceedings of WCET 2009.
  • Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms
    By Martino Ruggiero and others, University of Bologna.
    In: IEEE TCAD, 28 (3), 2009.
  • Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
    By Reinhard Wilhelm et al., Saarland University.
    In: IEEE TCAD, 28 (7), 2009.
  • Operating Mode Specific WCET Analysis
    By Philipp Lucas and others, Saarland University.
    In: Proceedings of JRWRTC 2009.
  • Optimal Static WCET-Aware Scratchpad Allocation of Program Code
    By Heiko Falk and others, TU Dortmund.
    In: Proceedings of DAC 2009.
  • WCET-Aware Register Allocation Based on Graph Coloring
    By Heiko Falk and others, TU Dortmund.
    In: Proceedings of DAC 2009.
  • Periodic Power Management Schemes for Real-Time Event Streams
    By Kai Huang and others, ETH Zurich.
    In: CDC 2009.
  • Power-Aware Mapping of Probabilistic Applications onto Heterogeneous MPSoC Platforms
    By Andreas Schranzhofer and others, ETH Zurich.
    In: Proceedings of RTAS 2009.
  • Proactive Speed Scheduling for Frame-Based Real-Time Tasks under Thermal Constraints
    By Jian-Jia Chen and others, ETH Zurich.
    In: Proceedings of RTAS 2009.
  • Thermal-Aware Global Real-Time Scheduling on Multicore Systems
    By Nathan Fisher, Wayne State University, Shengquan Wand, University of Michigan-Dearborn, and Jian-Jia Chen and Lothar Thiele, ETH Zurich.
    In: Proceedings of RTAS 2009.
  • The Space of EDF Deadlines: the Exact Region and a Convex Approximation
    By Enrico Bini and Giorgio Buttazzo, Scuola Superiore Sant’Anna.
    In: Real-Time Systems, 41 (1), 2009.
  • Throughput Constraint for Synchronous Data Flow Graphs
    By Alessio Bonfietti, Michele Lombardi, Michela Milano, and Luca Benini, University of Bologna.
    In: Proceedings of CPAIOR 2009.
  • Timing Predictability of Embedded Systems
    By Daniel Kästner, AbsInt.
    In: Embedded World Conference 2009.

2010

  • Adaptive Power Management for Real-Time Event Streams
    By Kai Huang, Jian-Jia Chen, and Lothar Thiele, ETH Zurich, and Luca Santinelli and Giorgio Buttazzo, Scuola Superiore Sant’Anna.
    In: Proceedings of ASP-DAC 2010.
  • Dynamic and Adaptive Allocation of Applications on MPSoC Platforms
    By Andreas Schranzhofer, Jian-Jia Chen, and Lothar Thiele, ETH Zurich, and Luca Santinelli, Scuola Superiore Sant’Anna.
    In: Proceedings of ASP-DAC 2010.
  • Automatic Selection of Machine Learning Models for WCET-Aware Compiler Heuristic Generation
    By Paul Lokuciejewski and others, TU Dortmund.
    In: Proceedings of SMART 2010.
  • Efficient OpenMP Data Mapping for Multicore Platforms with Vertically Stacked Memory
    By Andrea Marongiu and others, University of Bologna.
    In: Proceedings of DATE 2010.
  • Multi-Objective Exploration of Compiler Optimizations for Real-Time Systems
    By Paul Lokuciejewski and others, TU Dortmund.
    In: Proceedings of ISORC 2010.
  • WCET-Driven Cache-Aware Memory Content Selection
    By Sascha Plazar and others, TU Dortmund.
    In: Proceedings of ISORC 2010.
  • Reconciling Compilation and Timing Analysis
    By Heiko Falk and others, TU Dortmund.
    In: Advances in Real-Time Systems, 2010.
  • Timing Analysis for TDMA Arbitration in Resource Sharing Systems
    By Andreas Schranzhofer and others, ETH Zurich.
    In: Proceedings of RTAS 2010.
  • Worst-Case Delay Analysis for Memory Interference in Multicore Systems
    By Rodolfo Pellizzoni and Marco Caccamo, University of Illinois at Urbana-Champaign, and Andreas Schranzhofer, Jian-Jia Chen, and Lothar Thiele, ETH Zurich.
    In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2010.
  • Precomputing Memory Locations for Parametric Allocations
    By Jörg Herter and others, Saarland University.
    In: Proceedings of WCET’10.
  • Predictability Considerations in the Design of Multi-Core Embedded Systems
    By Christoph Cullmann and others, AbsInt.
    In: Proceedings of ERTSS’10.
  • Resilience Analysis: Tightening the CRPD Bound for Set-Associative Caches
    By Sebastian Altmeyer and others, Saarland University.
    In: Proceedings of LCTES’10.
  • Static Timing Analysis for Hard Real-Time Systems
    By Reinhard Wilhelm and others, Saarland University.
    In: Proceedings of VMCAI’10.
  • Superblock-Based Source Code Optimizations for WCET Reduction
    By Paul Lokuciejewski and others, TU Dortmund.
    In: Proceedings of ICESS’10.
  • Towards Precise PLRU Cache Analysis (PDF, 325kB)
    By Daniel Grund, Saarland University, and Jan Reineke, University of California, Berkeley.
    In: Proceedings of WCET’10.
  • Worst-Case Response Time Analysis of Resource Access Models in Multicore Systems
    By Andreas Schranzhofer, Jian-Jia Chen and Lothar Thiele, ETH Zurich, and Rodolfo Pellizzoni and Marco Caccamo, University of Illinois at Urbana-Champaign.
    In: Proceedings of DAC’10.
  • A Compiler Framework for the Reduction of Worst-Case Execution Times
    By Heiko Falk and others.
    In: Real-Time Systems, 46(2):251–300.

2011

  • A Template for Predictability Definitions with Supporting Evidence
    By Daniel Grund and others, Saarland University.
    In: Proceedings of PPES’11.
  • Software Structure and WCET Predictability
    By Gernot Gebhard, Christoph Cullmann, and Reinhold Heckmann, AbsInt.
    In: Proceedings of PPES’11.
  • Approximating Pareto Optimal Compiler Optimizations Sequences — a Trade-Off between WCET, ACET, and Code Size
    By Paul Lokuciejewski and others, TU Dortmund.
    In: Software: Practice & Experience.
  • Branch Target Buffers: WCET Analysis Framework and Timing Predictability
    By Daniel Grund and others, Saarland University.
    In: Journal of Systems Architecture.
  • Improving the Precision of WCET Analysis by Input Constraints and Model-Derived Flow Constraints
    By Reinhard Wilhelm and others, Saarland University.
    In: Advances in Real-Time Systems.
  • Reconciling Compilation and Timing Analysis
    By Heiko Falk and others, TU Dortmund.
    In: Advances in Real-Time Systems.
  • Timing Analysis for Resource Access Interference on Adaptive Resource Atibters
    By Andreas Schranzhofer and others, ETH Zurich.
    In: Proceedings of RTAS’11.